1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an input circuit for inputting signals.
2. Description of the Related Art
As an operating frequency of a chip including integrated circuits increases, an inter-chip interface scheme is being developed for high bandwidth and low power consumption thereof. Examples of general interface scheme include an interface scheme using AC Coupled Interconnection (ACCI) for high bandwidth and low power consumption and an interface scheme using a Current Mode Logic (CML)-type driver for high-speed operation.
FIG. 1 is a diagram illustrating an interface scheme using AC Coupled Interconnection (ACCI).
Referring to FIG. 1, an ACCI (AC Coupled Interconnection)-based interface scheme means a capacitive coupled input/output (I/O) circuit having a capacitor connected to a channel. In particular, a transmitter (TX) uses a voltage mode driver for power saving, and an output stage of the transmitter (TX) includes an impedance matching resistor for removing the influence of signal reflection. The ACCI-based interface scheme has band-pass characteristics of filtering off a DC component and passing an AC component and has a function of converting a Non-Return to Zero (NRZ) signal into a Return to Zero (RZ) signal.
FIG. 2 is a diagram illustrating an interface scheme using a Current Mode Logic (CML)-type driver.
Referring to FIG. 2, as compared to an ACCI (AC Coupled Interconnection)-based interface scheme, an interface scheme using a Current Mode Logic (CML)-type driver may provide a high-speed operation due to the CML-type driver.
However, the interface scheme using a CML-type driver has the following features.
The interface scheme using a CML-type driver has the features of duty cycle amplification causing the duty ratio of differential input signals (IN+, IN−) to be distorted while passing a channel, and it may be susceptible to a common mode noise. Here, the common mode noise means the phenomenon that a common mode voltage level of a differential signal swings and fails to maintain a target level.
Also, the interface scheme using a CML-type driver has the features of generating constant power consumption along a current path (P1, P2) when a differential signal is transmitted through a channel, as illustrated in FIG. 2.